Integrating Transputer Arrays within a Data-Flow Architecture: Applications in Real-Time Image Processing,, Olivier Ecklé, Georges M. Quénot and Jocelyn Sérot, Transputer'94, pages 135-152, France, 21-23 September, 1994.

This paper presents a Data Flow Functional Computer (DFFC) developed at ETCA and dedicated to real-time image processing. One original feature of this computer lies in the integration both at the hardware and software level of two types of data-driven processing elements: 1024 custom Data Flow Processor (DFP) -- embedded in a 3D interconnected network and dedicated to low level processing and 36 T800 Transputers -- embedded in a 2D interconnected networks and dedicated to mid to high level processing. A unifying programming model is provided, based on a close integration of the data-flow architecture principles and the functional programming concepts.
An image processing algorithm, expressed using an FP-like functional syntax is first converted into a Data-flow Graph (DFG). The nodes of this graph are real time operators implementable on the physical processors of the data-flow machine. This DFG is then physically mapped onto the network of processors.
The programming environment includes a complete compilation stream from FP-specification to hardware implementation, along with a global operator database. An original programming technique has been developed for the transputers to ensure a full compatibility with data-flow model. Several image processing algorithms were implemented on this system and run in real time at digital video speed.