Programming parallel architectures dedicated to real-time image processing (IP) is often a difficult and error-prone task. This mainly results from the fact that IP algorithms typically involve several distinct processing levels and data representations and that various models of execution as well as complex hardware are needed for handling these processings layers under real-time constraints.
Our goal is to allow an intuitive but still efficient use of such an architecture by providing a continuous and readable path from the functional specification of an algorithm to its corresponding hardware implementation.
For this, we came up with a data-flow programming model which can act simultaneously as a functional expression of algorithms and as a structural description of their corresponding implementations on a target computer built up of 3D interconnected data-driven processing elements (DDPs).
Algorithms are decomposed into functional primitives viewed as top-level nodes of a data-flow graph (DFG). Each node has a known physical implementation on the target architecture either as a single DDP or as an encapsulated sub-graph of DDPs, making the well-known mapping problem a topological one.
The target computer was built at ETCA and embeds 1024 custom data-driven processors and 12 transputers in a 3D interconnected network. Concurrently with the machine, a complete programming environment has been developed. Relying upon a functional compiler, a large library of IP primitives and automatic place-and-route facilities, it also includes various X-Window based tools whose goal is to allow visual and efficient access to all intermediary program representations.
The whole system has proven to be an invaluable platform for the fast design and prototyping of a wide range of vision applications operating in real-time on digital video streams.