A Dynamic Programming Processor for Speech Recognition, Georges M. Quénot, Jean-Luc Gauvain, Jean-Jacques Gangolf and Joseph J. Mariani, IEEE Journal of Solid-State Circuits, 24(2):349-357, April 1989.

An integrated processor dedicated to the computation of spectral distances and dynamic programming equations for speech recognition systems has been designed. Its 10 MIPS power allows real time recognition of 1,000 isolated words or 300 connected words with algorithms based only on dynamic programming and up to 5,000 isolated words with hierarchical recognition or 600 connected words using pruning techniques. Its flexibility makes it useful for a wide variety of dynamic programming algorithms. A system may use many of them in parallel, each with a local working memory plus a common memory for fast data exchange among them.
The chip has been processed in a 2 microns CMOS technology, includes 127,309 transistors in a 60 mm2 area, runs with a 20 MHz clock and is delivered in an 84-pin PGA or PLCC package. The design includes a hand-optimised layout for the datapath and the clock generator, a compiled standard-cell block for the control logic, a standard-cell based padring, and a compiled RAM.
Standard tests with NATO/Pannel III/RSG10 group tapes have been carried out on a system with one DP processor. Tests have been completed for 11 speakers in a set of 19. 3,000 isolated words have been recognized without any error and 2,850 chains of from 3 to 5 connected words with only 31 errors. The error rate is null for isolated words, of 1.08 % for connected words and of 0.53 % for the average. Those rates are significantly better than any others in the literature. Results are also shown for various applications including the recognition of 5,000 isolated words and the recognition of numbers from 0 to 9,999 with a speaker-independant syntax-constrained connected word recognition system.