A chip featuring two coupled data-flow processors (DFPs)
has been designed. It is to be mesh-connected into large processor arrays
dedicated primary to image processing. Each processor operates on 25 MBytes/s
data-flows and performs up to 50 million 8- or 16-bit arithmetic operations per
second. The chip has been processed in a 1 micron CMOS technology. It includes
160,000 transistors in a 84 mm2 die size area, its clock is at 25 MHz and
it is packaged in a 144-pin PGA package.
Computations are performed on the fly on pixel data-flows coming from digital video cameras. One physical operator is associated to each operation involved in the algorithm.
An experimental data-flow computer including 1024 processors in a 8 x 8 x 16 3D network has been built. Several significant image processing algorithms were successfully implemented in real-time.