Systematic Design of Image Processing ASICs through Real-Time Emulation, Ivan C. Kraljic, Francois Verdier, Georges M. Quénot and Bertrand Zavidovique, Eleventh International Conference on Systems Engineering, Las Vegas, USA, 9-11 July 1996.

A complete environment for designing real-time image processing VLSI circuits is presented. At the core of the methodology resides a dedicated emulator, the Data-Flow Functional Computer (DFFC), whose peak capacity is 20 million gates operating at 25 MHz. Applications are firstly validated in their target environment (real time, real-world scenes) during emulation on the DFFC. Two integration methods are then available: derivation and synthesis. The derivation method optimizes the architecture validated on the emulator, while the synthesis approach is not constrained by the emulator architecture, and thus allows to generate other (optimized) architectures.