A Reconfigurable Compute Engine for Real-Time Vision Automata Prototyping, Georges M. Quénot, Ivan C. Kraljik, Jocelyn Sérot and Bertrand Zavidovique, IEEE Workshop on FPGAs for Custom Computing Machines, pages 91-100, Napa Valley, CA, USA, April 10-13, 1994.

This paper describes a Reconfigurable Compute Engine (the Data-Flow Functional Computer, or DFFC) developed at ETCA and dedicated to rapid prototyping of real-time vision automata. The Computer consists of a regular 3D array of very coarse grain application-specific FPGA called the Field-Programmable Operator Array (FPOA); each FPOA includes 2 Configurable Data-Paths (CDP) and 10 Input/Output Ports (IOP). Specific development tools allow an easy and efficient use of the Computer: a high-level description (in a functional language) is compiled into a DFFC configuration using an Operator Library. Several significant applications (connected component labeling, colored object tracking) have been implemented using our tools. An environment for automatic derivation of vision automata from a DFFC configuration is currently under development.