A Data-Flow Processor for Real-Time Low-Level Image Processing, Georges M. Quénot and Bertrand Zavidovique, IEEE Custom Integrated Circuits Conference, pages 12.4.1-4, San-Diego, CA, USA, 13-16 May 1991.

A chip featuring two coupled data-flow processors (DFPs) has been designed. It is to be mesh-connected into large processor arrays dedicated primary to image processing. Each processor operates on 25 MBytes/s data-flows and performs up to 50 million 8- or 16-bit arithmetic operations per second. The chip has been processed in a 1 micron CMOS technology. It includes 160,000 transistors in a 84 mm2 die size area, its clock is at 25 MHz and it is packaged in a 144-pin PGA package.
Our approach is to perform computations on the fly on a data-flow that comes from a digital video camera and to associate one physical operator to each involved in an algorithm. The set of available operators on the DFP has been defined to cover as widely as possible the range of low-level image processing functions.