A Dynamic Programming Processor for Speech Recognition, Georges M. Quénot, Jean-Luc Gauvain, Jean-Jacques Gangolf and Joseph Mariani, IEEE Custom Integrated Circuits Conference, pages 10.5.1-4, Rochester, NY, USA, 16-19 May 1988.

An integrated processor dedicated to the computation of spectral distances and dynamic programming equations for speech recognition systems has been designed. Its 10 MIPS power allows for real time recognition of 1000 isolated words and 300 connected words with a fully optimal method. Its flexibility makes it useful for a wide variety of dynamic time warping algorithms.
The chip has been processed in a 2 um CMOS technology, includes 127309 transistors in a 60 mm2 area, runs with a 20 MHz clock and is delivered in an 84-pin PGA package. The design includes a fully optimized layout for the datapath and the clock generator, a standard cell approach for the control logic and the padring, and a compiled RAM.