Investigating Real-TimeValidation of Real-Time Image Processing ASICs, Ivan C. Kraljic, Francois S. Verdier, Georges M. Quénot and Bertrand Zavidovique, Int'l Workshop on Computer Architectures for Machine Perception, Cambridge, Mass., USA, 20-22 Oct 1997.

The research presented in this paper aims at designing real-time image processing Application Specific Integrated Circuits (ASICs), with emphasis on the need for correct circuits. The methodology is based on a dedicated emulator, the Data-Flow Functional Computer (DFFC), whose peak capacity is 20 million gates operating at 25 MHz. Applications are firstly validated in their target environment (real time, real-world scenes) during emulation on the DFFC. Two integration methods have been implemented: derivation and synthesis. The derivation method optimizes the architecture validated on the emulator, while the synthesis approach is not constrained by the emulator architecture, and thus allows to generate other (optimized) architectures.