A Functional Data-flow Architecture dedicated to Real-time Image Processing Jocelyn Sérot and Georges M. Quénot, International Workshop on Computer Architecture and Machine Perception, pages 33-44, Paris, France, 16-18 December 1991.

This paper describes a massively parallel data-flow computer dedicated to real-time image processing. This computer which embeds two regular arrays of respectively low and high level processing elements reflects at the hardware level the general duality that exits between low and high level computations in many image processing algorithms. In our approach, such algorithms, first expressed using an FP-like functionnal syntax are converted into Data-Flow Graphs in which the nodes are real time operators implementable on the physical processors of the data-flow machine. A first computer embedding 128 custom data-flow processors and one transputer has been build and achieve real time processing of data flows coming from a video camera. A basic target following algorithm has been implemented and runs sucessfully at 25 Mhz pixel frequency on 512 x 512 images. A coherent graphic programming environment, will allow image processing specialists, which could not be aware of computer architecture to design, implement and test a wide range of real time processings.