A Data-Flow Processor for Real-Time Low-Level Image Processing, Georges M. Quénot and Bertrand Zavidovique, EURO ASIC Conference, pages 92-95, Paris, France, 28-31 May 1991.

A chip featuring two coupled data-flow processors (DFPs) has been designed. It is to be mesh-connected into large processor arrays dedicated primary to image processing. Each processor operates on 25 MBytes/s data-flows and performs up to 50 million 8- or 16-bit arithmetic operations per second. The chip has been processed in a 1 micron CMOS technology. It includes 160,000 transistors in a 84 mm2 die size area, its clock is at 25 MHz and it is packaged in a 144-pin PGA package.
Computations are performed on the fly on a data-flow that comes from a digital video camera. One physical operator is associated to each operation involved in the algorithm.
An experimental data-flow system including 8 processors in a 2 x 2 x 2 3D network has been built. Edge detection, row sums, column sums and histograms have been implemented on it at digital video speed.