A Wavefront Array Processor for on the Fly Processing of Digital Video Streams, Georges M. Quénot, Christophe Coutelle, Jocelyn Sérot and Bertrand Zavidovique, International Conference on Application-Specific Array Processors, Venice, Italy, 25-27 October, 1993.

We present a wavefront array processor architecture developed at ETCA and dedicated to real-time processing of digital video streams. The core of the architecture is a mesh-connected three-dimensional network of 1024 custom processing elements. Each processing element can perform up to 50 millions 8- or 16-bit operations per second, working with a 25 Mhz clock frequency. Thus the theoretical peak power of the machine is 50 billions operations per second. Mapping of complex algorithms is facilitated by the routing capabilities of each processing element.
The machine is fully data-driven and is a ``pure'' data-flow one since there are no address flows. Algorithms and architecture are described using a data-flow graphs formalism. Image processing applications are decomposed into elementary operators that correspond to physical processors in a one to one fashion. Several algorithms can be simultaneously mapped and independently executed on the processor network.
Referring to the academic wavefront array paradigm, ``exotic features'' are exhibited. They are related to the wavefront propagation mode at run-time and to the heterogeneous nature of data-flows that are piped into or from the processor network. These features are shown to make the architecture well-suited for fast prototyping of low-level image processing automata.